1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device including fuse elements.
2. Description of the Related Art
Voltage regulators and voltage detectors each include an analog processing circuit, a logic circuit, a capacitor, a bleeder resistor, and the like. In the bleeder resistor, there are formed fuse elements for selecting resistors so that voltage may be adjusted to a desired one in an inspection step.
An example of such a conventional semiconductor integrated circuit device is described with reference to FIGS. 4, 5, and 6. FIG. 4 is a plan view of the fuse elements. FIG. 5 is a sectional view including a cross section taken along the line A-A′ of FIG. 4 and a MOS transistor and a resistor 512 that are arranged on both sides thereof. FIG. 6 is a sectional view taken along the line B-B′ of FIG. 4. As illustrated in FIG. 5, fuse elements 405 are formed on an element isolation insulating film 503, and are formed of a polycrystalline Si film doped with impurities, which is the same conductive material as a gate electrode 405a of the MOS transistor.
The polycrystalline Si films 405 are covered with an interlayer insulating film 513 and a BPSG film 514 serving as a flattening film. Contact holes 415 reaching vicinities of both end portions of the polycrystalline Si film are opened within the BPSG film 514 and the interlayer insulating film 513. On the BPSG film 514, wirings formed of a first aluminum film 416 are patterned so that the wirings are brought into contact with the polycrystalline Si film 405 through the contact hole 415 illustrated in FIG. 4. The aluminum films 416 are covered with a first metal interlayer insulating film 518 formed of TEOS as a raw material by plasma CVD.
In the conventional example, a second aluminum film (not shown) is also used in addition to the first aluminum film 416. Therefore, as a flattening film between those aluminum films, SOG films 519 are formed on the first metal interlayer insulating film 518 by rotation coating, curing, and etch-back thereafter. The SOG films 519 are covered with a second metal interlayer insulating film 520, which is formed of TEOS as a raw material by plasma CVD. The second metal interlayer insulating film 520 is covered with an SiN film 521 serving as an overcoat film formed by plasma CVD.
Besides, on the polycrystalline Si films 405, there is formed an opening region 422 for cutting with a laser beam the polycrystalline Si film 405 serving as the fuse element. The opening region 422 is formed by etching using the same mask used for etching the SiN film 521 on an aluminum pad (not shown) at the same time. However, due to over etching, the opening region 422 reaches the first metal interlayer insulating film 518. Because the fuse opening region 422 reaches the first metal interlayer insulating film 518 as described above, the SOG films 519 for flattening the surface of the first metal interlayer insulating film become a passage for moisture to enter an internal element of the semiconductor integrated circuit from the outside due to water or vapor, which has caused poor long-term reliability of the semiconductor integrated circuit device. In particular, in a PMOS transistor, a threshold voltage shift of the transistor occurs when a negative gate bias is applied, which has caused a problem of negative bias temperature instability (NBTI).
As a measure to prevent such deterioration in long-term reliability due to moisture entrance from the fuse opening region 422, there has been introduced a structure in which a seal ring 417 is formed at the outer periphery of the fuse opening region so as to form a barrier of the first aluminum film, to thereby prevent entrance of moisture inside the IC (for example, see Japanese Patent Application Laid-open Nos. Hei 05-021605 and Hei 07-022508).
However, in the seal ring 417 formed of the first aluminum film as the barrier for preventing moisture entrance from the fuse opening region 422, due to the step difference caused by presence and absence of the fuse elements 405 formed of the polycrystalline Si film as illustrated in FIGS. 5 and 6, the seal ring 417 has regions with a lower height. As a result, as illustrated in FIGS. 5 and 6, in the conventional structure, the SOG films 519 above the seal ring 417 cannot be sufficiently removed at the time of etch-back, with the result that the SOG film 519 present at the inner surface of the fuse opening region 422 and the SOG film 519 on the internal element side are connected to each other as a passage for the moisture, which may cause deterioration in characteristics of the IC.